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-- Company: 
-- Engineer: 
-- 
-- Create Date:    18:53:45 11/24/2009 
-- Design Name: 
-- Module Name:    Datapath - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity IR is
    Port ( Opcode : out  STD_LOGIC_VECTOR (31 downto 26);
           rs : out  STD_LOGIC_VECTOR (25 downto 21);
           rt : out  STD_LOGIC_VECTOR (20 downto 16);
           rd : out  STD_LOGIC_VECTOR (15 downto 11);
           shift : out  STD_LOGIC_VECTOR (10 downto 6);
           funct : out  STD_LOGIC_VECTOR (5 downto 0);
           Instruction : in  STD_LOGIC_VECTOR (31 downto 0);
			  clk : in STD_LOGIC);
end IR;

architecture Behavioral of IR is

begin
   info : process is
	begin
		Opcode <= Instruction (31 downto 26);
		rs <= Instruction (25 downto 21);
		rt <= Instruction (20 downto 16);
		rd <= Instruction (15 downto 11);
		shift <= Instruction (10 downto 6);
		funct <= Instruction (5 downto 0);
	end process info;		

end Behavioral;

